Pulse width comparator



United States Patent O 3,313,927 PULSE WIDTH COMPARATOR Ronald R. Raike, Endweil, and Hermann Schmid, Binghamton, N.Y., assgnors to General Electric Company, a corporation of New York Filed Oct. 10, 1963, Ser. No. 315,230 2 Claims. (Cl. 23S- 177) This invention relates to data processing circuits for comparing a pair of pulse width modulated signals and deriving information signals indicative of which of the compared signals is greater. T-he present invention is particularly concerned with the elds in which analog computers have been traditionally employed such as in navigation computers, re control systems, autopilots, and similar systems. It is applicable to ydata processing of the type in which information quantities are represented by a train of pulses, the pulses occurring during respective system cycles of tixed duration. The pulses are synohronized, normally starting at the beginning of each cycle and terminating after ya time interval proportional to the magnitude of the variable being represented in accordance with the system scale factors. The pulses are in the form of voltage waveforms having two levels, one of which represents the presence of a pulse.

In computers and control systems, particularly for realtime d-ata processing, an important operation is the comparison of two variable quantities. While this operation is conceptually simple, in terms of eicient and practical circuits, the realization of comparison operations is usually difficult. A comparison normally requires information lboth as to the amount of the difference and as to which quantity is larger. In many data processing systems, this information can be represented by a single signal, such as a voltage, Iwhere the signal amplitude represents the difference and the signal sign indicates the larger variable. However, in pulse width systems, the pulses usually have a single polarity so that a separate output signal is required to establish which variable is larger.

A natural approach to lpulse width comparison is to subtract one pulse from the other. The resultant pulse width signal becomes smaller and smaller as the compared signals approach equal pulse widths but the signal describing which quantity is larger is constant. The desired information involved in comparing two pulse width signals to determine which is larger is actually a discontinuous function. It has one value when the rst signal is larger and another value when t-he first signal is smaller. Where two signals are subtracted, the resultant signal is a continuously variable signal which is proportionately sensitive to the pulse width difference. This results in undesirable gain demands on circuitry implementing the subtraction operation and also on the circuitry responsive to t-he resultant comparison signals.

Accordingly, it is `an object of the invention to provide a pulse width comparator in which the output signal representing which input pulse width signal is greater is not proportional to the pulse width differential.

It is another object of the invention to provide a pulse width comparator which directly compares the input signals with economical circuitry utilizing standard subcircuits and providing high precision operation.

Briefly stated, in accordance with certain objects of the invention, a pulse width comparator is provided with utilizes digital logic type circuits. It has been found that by treating the variable analog pulse width signals such as x and y as digital signals and forming the terms Ey and x7] of the exclusive OR sum, a pair of signals are produced which represent the amount each signal exceeds t-he other, in ,pulse width form. The exclusive "ice OR term signals are applied to a digital flip-flop circuit which t-hen produces a signal representing which quantity is greater. When ,generating the input signal synchronously, the exclusive OR term signals represent the appropriate :arithmetic difference by their pulse durations and do not require gating. The output signal representing which input is larger is appropriately discontinuous, having high gain.

These and other objects and features of the present invention will become apparent from the accompanying detailed description and drawings in which:

FIGURE l is la 4block diagram of a tirst embodiment of the invention.

FIGURE 2 is a series of waveforms illustrating the operation of the FIGURE l comparator.

FIGURE 3 is a block diagram of a second embodiment of the invention.

Referring now to the drawings, FIGURE l illustrates a rst embodiment of the comparator invention in block diagram form. A pair of analog signal sources 11 and 12 produce pulse width modulated signals which are proportional to quantities x and y respectively. These signals can represent common analog computer or analog control signals such as, for example, in servo-mechanisms in which x is a signal representing the control quantity and y is a signal representing the feed-back quantity. These x and y signals are com-pared by logic operations and with digital computer type circuits. For the logic operations, the complements of the input quantities are obtained by inverters 13 and 114 which are coupled to the input sources 11 and 12 respectively. The ouputs of inverters 13 and 14 `are a train of pulses in which the pulse durations are inversely proportional to x and y durations, that is, the outputs are the complements 'ab' and i] in respect to the full scale range of x and y, although not in phase with the x and y signals. The logic operations are performed by a pair of "AND gates 15 and 16 which produce signals representing 5y and x@ respectively in response to the signals produced by signal sourcesjll and 12 and inverters 13 and 14. These 5y and xi] signals are then applied to the reset and set inputs of set-reset flip-flop 17. As a result, output signals are provided by flip-Hop 17 such t-hat a O state signal on the normal l output represents the conditions x y, and the lf state signal represents the x y condition. In the process of this comparison, the comparator also makes available convenient pulse width signals which have a time dura.'- tion proportional to the difference between the x and y quantities. These signals are the outputs of the and gates 15 and 16 which are x@ and Ey, respectively. These two output signals Iare in effect gated, in that each one produces no diiference output if the other does. Accordingly, these output signals can be used directly such as for unidirectional motor control, or as an x-y (or y-x) input to further data processing apparatus.

FIGURE 2 presents a series of waveforms illustrating the operation of the FIGURE l comparator. Initially, with the x quantity from input source 11 greater than the y q-uantity from source 12, the inverter 114 output waveform i] overlaps the x waveform and the inverter 13 waveform E does not overlap y. Therefore, AND gates 15 and 16 whic-h are respectively responsive to these conditions produce signals representing the overlap conditions. From a logic point of view, gate 15 produces a l output during the overlap period representing xij, while gate 16 produces a O (or no pulse) signal representing 5y. The flip-flop 17 in response to these signals is in a reset condition with a 0 output indicating that the x input signal is greater than the y input signals. As x and y quantities change, the flip-flop 17 changes to the l state when y becomes greater than x because gate 1-6 produces an appropriate set signal. That is, the inverter 13 signal 'ai overlaps the input signal y and gate 15 no longer produces a signal which can reset flip-flop 17. It will be noted that the AND" gate outputs x and 5y are mutually exclusive. Therefore, flip-flop 17 can produce continuous output signals which indicate whether x or y is ygreater in accordance with the last overlap signal.

In the above description, the outputs of inverter 1 3 -and 14 are signals which do not truly represent E and in the same sense as the input signals represent x and y. Essentially, this is because 5 and 7 are not synchronized with x and y. Pulse width modulation, of the type considered here, is based on a system in which pulses represent quantities by having la duration, from the beginning of a pulse cycle, which is proportional to these quantities. However, as can :be seen from an inspection of the FIGURE 2 waveforms, the desired output quantities are obtained by treating the input analog waveforms as if they were digital signals in the manner described.

In implementing the FIGURE 1 comparator, the selection of circuitry for inverters 13, 14, and gates 15, 16 and flip-flop 17 is preferably from economical conventional types. At the present time, solid state circuits utilizing semiconductor lactive devices lprovide the best overall characteristics. Performance characteristics of the comparator are primarily determined by the switching speeds of the active devices. With the use of integral packaged circuits for the various digital logic circuits, the comparator is readily implemented with minimum bulk. An example of implementation for the x and y input sources 11 and i12 is the use of standard counters. If digital input signals representing x and y are introduced into the respective counters and a clock source counts down, the counters will generate 'appropriate pulse width signals. With this implementation, the pulse width comparator operates as a `digital comparator having far less cornplexity than standard digital comparators.

FIGURE 3 illustrates a second embodiment of the invention. In this embodiment, output nip-flop 34 provides signals representing which input is larger as does flip-flop 17 in the first embodiment. The operation can be more readily understood as being one responsive to t-he order in which the x and y pulses terminate. The flip-op 31 is of an Eccles-Jordan type which has its set and reset inputs coupled respectively to the x and y input sources 11 and 12 in the usual manner. That is, because of internal feedback and capacitive coupling of the input signals, ip-op 31 is only responsive to the trailing edges in the input pulse trains. At the beginning of each steady state cycle, the ip-fiop 31 will either be in the l state or the O state, depending upon which pulse, x or y, terminated last during the preceding cycle. At the termination of the shorter input pulse, Hip-flop 31 is switched to the opposite state and, at the termination of the longer input pulse, it is switched again, back to the state at the beginning of the cycle (assuming relative magnitudes remain unchanged). In order to sense which state occurs last, ip-flop 34 is coupled to the respective l and 0 outputs of ip-o-p 31. With the usual negative logic at these outputs, a lower level voltage is produced at. the l output for a l state, and a lower level voltage is produced-at the complement or 0 output for :a 0 state. When a clock (or sample) pulse is applied to the ip-op 34 in the usual manner at the end of each cycle, the appropriate logic signals are produced for switching output flip-flop 34 to the same state as input flap-hop 31, thereby sampling its condition.

T'he FIGURE 3 embodiment also produces pulse width signals representing the difference between the x and y inputs. These signals are generated by the input ipop 31 at its output terminals. In utilizing the signals, one of which is the desired exclusive OR term, it is necessary that recognition be made of their negative logic nature as generated by an Eccles-Jordan iiip-op 31 and that the flip-flop 34 be used to provide the appropriate selection information.`

The 'above embodiments of the invention have similar advantages. No anaiog process can be performed more accurately t-hat the comparison of two time events. The trailing edges of two pulses constitute two such time events. The accuracy with which the difference between two pulse width signals can vbe measured is a function of the delay time, rise time, storage time and fall time of these pulses and of how =much noise (ripple) there is on these pulses. With present art digital switching circuits, total switching times of less than nanoseconds are easily possible. Comparing this constant noise amplitude of 100 nanoseconds with the repetition period indicates the full scale accuracy. Higher accuracies rare, however, always possible by decreasing the switching time or by increasing the repetition time. A decrease in switching time reques higher speed and usually more expensive components. Also, there is a limit as to how much the switching time can be decreased. However, there is no limit as to how much the repetition period can be increased. The larger the .repetition period, the longer it takes to get the desired information. As usual, speed of operation must be sacrificed for accuracy.

While particular embodiments of the invention have been shown and described herein, it is not intended that the invention be limited to such disclosure, but that changes and modifications can be made and incorporated within t-he scope of the claims.

W-hat is claimed is:

1. A pulse width comparator comprising:

(a) a first source of input signals representing a first information quantity such as x by p-ulse width modulation;

(b) a second source of input signals representing a second information quantity such as y by pulse width modulation which provides signals in synchronism with said x pulses;

(c) first and second inverters responsive to said first and second input sources for producing the inverted signals E and 5;

(d) a rst AND gate, responsive to said irst input source and said second inverter throughout a cycle of the input signals, for producing a first exclusive OR term signal 5y;

(e) a second AND gate, responsive to said second input source and said rst inverter throughout the cycle of the input si-gnals, for producing the second exclusive OR term signal xg-j; and

(f) `a set-reset flip-flop, responsive to said iirst and second AND gates, for producing a bistable output signal indicative of which input signal is greater, x y or x y.

2. A pulse width comparator comprising:

(fa) first and second sources of synchronized input signal pulse trains representing variable x and y quantities by pulse width modulation;

(b) an Eccles-Jordan flip-flop having set and reset inputs, respectively coupled to said x and y input signals, and having 1 and 0 outputs;

(c) an output ip-iiop having its set and reset inputs responsive to the l and 0 outputs of saidEccles- Jordan Hip-flop for producing signals representing x y and y x; and

(d) sampling means for effectively gating the input to said output flip-flop at the end of each cycle of the pulse train only.

References Cited by the Examiner UNITED STATES PATENTS 2,900,620 8/1959 Johnson S40- 146.2

ROBERT C. BAILEY, Primary Examiner'.

G. D. SHAW, Assistant Examiner. 

1. A PULSE WIDTH COMPARATOR COMPRISING: (A) A FIRST SOURCE OF INPUT SIGNALS REPRESENTING A FIRST INFORMATION QUANTITY SUCH AS X BY PULSE WIDTH MODULATION; (B) A SECOND SOURCE OF INPUT SIGNALS REPRESENTING A SECOND INFORMATION QUANTITY SUCH AS Y BY PULSE WIDTH MODULATION WHICH PROVIDES SIGNALS IN SYNCHRONISM WITH SAID X PULSES; (C) FIRST AND SECOND INVERTERS RESPONSIVE TO SAID FIRST AND SECOND INPUT SOURCES FOR PRODUCING THE INVERTED SIGNALS $ AND $; (D) A FIRST "AND GATE," RESPONSIVE TO SAID FIRST INPUT SOURCE AND SAID SECOND INVERTER THROUGHOUT A CYCLE OF THE INPUT SIGNALS, FOR PRODUCING A FIRST "EXCLUSIVE OR" TERM SIGNAL $Y; (E) A SECOND "AND GATE," RESPONSIVE TO SAID SECOND INPUT SOURCE AND SAID FIRST INVERTER THROUGHOUT THE CYCLE OF THE INPUT SIGNALS, FOR PRODUCING THE SECOND "EXCLUSIVE OR" TERM SIGNAL X$; AND (F) A SET-RESET FLIP-FLOP, RESPONSIVE TO SAID FIRST AND SECOND "AND GATES," FOR PRODUCING A BISTABLE OUTPUT SIGNAL INDICATIVE OF WHICH INPUT SIGNAL IS GREATER, X>Y OR X<Y. 